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AI Edge

NVIDIA expands NVLink Fusion with NVHBM to boost AI chip performance

NVIDIA today launched NVLink Fusion with NVIDIA NVHBM, a custom high-bandwidth memory technology that delivers up to 30% more memory bandwidth and 15% lower power use while freeing 25% of XPU die space.

Source: NVIDIA Newsroom · August 26, 2026 at 9:31 PM · AI-assisted report

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NVIDIA expands NVLink Fusion with NVHBM to boost AI chip performance
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KUALA LUMPUR, 27 AUGUST 2026 —

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NVIDIA today launched NVLink Fusion with NVIDIA NVHBM, a custom high-bandwidth memory technology that delivers up to 30% more memory bandwidth and 15% lower power use while freeing 25% of XPU die space.

Market Impact

The Santa Clara chipmaker said NVHBM moves the memory controller from the XPU die into the 3D HBM stack, cutting engineering time and standardising memory across multiple suppliers. Amazon’s Annapurna Labs will be the first partner to adopt NVHBM, working with NVIDIA on next-generation Trainium4 accelerators that will slot into a shared rack-scale fabric.

“NVHBM represents a new architectural approach to advancing high-bandwidth memory performance and efficiency,” said Nafea Bshara, vice president of Annapurna Labs at Amazon. “We look forward to this technology collaboration to benefit future AWS infrastructure designs.”

NVIDIA markets NVLink Fusion as a rack-scale platform where partners can license NVLink chiplets, NVLink-C2C interfaces, NVLink Switches and NVIDIA MGX systems. The platform also plugs into an ecosystem of CPU vendors, ASIC designers and system builders, letting hyperscalers and AI-native firms focus engineering budgets on XPU innovation instead of memory integration.

By offering a single standard for NVHBM across suppliers, NVIDIA aims to cut the time and cost of qualifying memory on custom accelerators. The company said this lowers the barrier for partners to bring semi-custom AI chips to market using proven networking, chassis and software stacks.

The move comes as hyperscalers push larger models and agentic workloads that strain current AI accelerators. NVIDIA argues tighter coupling of memory, networking and compute is now essential to sustain throughput and energy efficiency at trillion-parameter scale.

For Malaysian technology investors, the announcement signals growing demand for NVLink-compatible boards and rack systems as hyperscalers localise AI infrastructure in Southeast Asia.

Related: NVIDIA · Nafea Bshara · Kuala Lumpur

Reporting based on NVIDIA Newsroom. Figures and claims are subject to revision as the story develops. DomainFork publishes editorial context, not investment advice — see our editorial standards.