TSMC’s second-quarter earnings set to test AI infrastructure limits

KUALA LUMPUR, 23 JULY 2026 —

TSMC reports second-quarter earnings on July 16 with Wall Street expecting revenue near $40 billion, up roughly 32% year-over-year, and earnings per ADR unit to rise more than 50% from a year ago.

Analysts say the key takeaway will be whether management raises full-year revenue guidance above the current “above 30%” range or lifts the 2026 capital budget beyond the $52 billion to $56 billion corridor. A third focus is an update on CoWoS advanced packaging, the current bottleneck in AI chip production.

TSMC itself guided to revenue between $39.0 billion and $40.2 billion and gross margin in a 65.5% to 67.5% range. Combined April and May revenue grew about 24% year-over-year, short of the roughly 35% some investors penciled in, introducing near-term jitters despite the longer-term growth story remaining intact.

The company is central to the AI buildout, fabricating components for Amazon, Microsoft, Alphabet and Meta, which together plan to spend about $700 billion on capital expenditure this year, up roughly three-quarters from 2025. Nearly every leading AI accelerator—Nvidia’s GPUs, AMD’s MI-series chips, and custom ASICs from Google and Amazon—is made on TSMC’s advanced nodes and finished in TSMC’s packaging lines.

Industry trackers estimate the supply-demand gap for CoWoS could narrow from about 20% earlier this year to roughly 10% by the end of 2026 as TSMC adds capacity in Tainan, Chiayi and Arizona. Nvidia alone has reportedly secured roughly 60% of TSMC’s CoWoS output for 2026, pushing other GPU and ASIC makers to supplement capacity at Samsung.

TSMC’s Arizona expansion, framed as an $465 billion, eleven-fab program, faces practical constraints including water availability, visa delays for Taiwanese engineers and long-term power supply, according to Taiwan’s National Development Council. Any one of these could push fab timelines by quarters or years.

TSMC told major customers including Apple, Nvidia and Qualcomm to expect a fourth consecutive year of price increases starting in 2026, with hikes running 3% to 10% depending on the node and application. A 2-nanometer wafer now costs more than $30,000, over 50% above a 3-nanometer wafer, and TSMC guided to 2-3 percentage points of gross margin dilution from the 2-nanometer ramp and overseas expansion.

For now, Nvidia’s wide margins allow it to pass costs through, but smartphone and PC chipmakers operating on thinner margins are expected to pass some increases to consumers, which analysts say will lift flagship device prices later this year.

Wherever the numbers land, TSMC remains at the technological frontier, commanding the most desirable customer allocations and a “trust moat” built on years of meeting commitments.

Related: TSMC